1. Field of the Invention
The present invention relates to a method for manufacturing a merged DRAM with a logic (MDL) device, and more particularly to a method for forming a high-capacity DRAM capacitor.
2. Description of the Prior Art
In recent years, much interest has been drawn to a semiconductor device having a DRAM and a logic device integrated on a single chip. This is because the integration of the DRAM and the logic device on the single chip allows a high-speed driving at a low rate of power consumption in comparison with conventional chips. However, the semiconductor device has a drawback in that, with respect to the integration of the DRAM and the logic device on the single chip, the size of a chip is increased, the manufacturing process is complicated, and manufacturing yield is low.
A semiconductor device having a DRAM and a logic device on the single chip is usually called an embeded DRAM from the standpoint of DRAM, and a merged DRAM with a logic (MDL) device from the standpoint of logic devices. Such a semiconductor device, however, is hereinafter uniformly referred to as an MDL device.
An MDL device can be formed by two methods, one an adaptation of a logic process based on a DRAM process and the other an adaptation of a DRAM process based on a logic process. However, these methods both have drawbacks in that a thermal budget due to a capacitor process of a DRAM is considerably larger than that due to a logic process, thus adversely affecting performance of logic, and also in that Ti or Co-silicide adapted to a logic process of below 0.25 μm is agglomerated to cause a junction leakage and a resistance increase of gate electrode.
Accordingly, in order to solve these problems, MDL devices have been conventionally manufactured the same way as in the logic process by adapting a flat capacitor adapted to DRAM of below 1M, to the DRAM capacitor.
The conventional method for manufacturing an MDL device will be now described with reference to FIGS. 1A to 1D.
Referring now to FIG. 1A, an isolation layer 2 is formed on a field region of a semiconductor substrate 1 in accordance with a known shallow trench isolation (STI). Then, an ion implantation process for a formation of well and a control of threshold voltage (Vt) is carried out in a state in which a mask 3 for ion implantation is formed on a certain portion of the substrate 1.
Referring to FIG. 1B, after the mask for ion implantation is removed, a gate oxide layer 4 and a gate conductive layer 5 are formed one by one. The layers 4 and are patterned to form gate electrodes 6. Herein, upon patterning the gate conductive layer 5 and the gate oxide layer 4, the layers 5 and 4 are left even on a substrate region on which a capacitor is formed. The resultant laminated layers serve as a dielectric and a node, respectively, of the MDL device manufactured, thus making up a flat capacitor.
Successively, a lightly doped drain (LDD) ion implantation and a halo ion implantation are conducted to the resultant of the substrate to form an LDD region 7 on the substrate surface between the gate electrodes 6 and a halo region 8 on the substrate surface below an edge portion of the gate electrode.
Referring to FIG. 1C, an insulating layer is deposited on the resultant of the substrate and then a blank etch is performed thereto thus to form a spacer 9 to both sidewalls of the gate electrode. Then, a source/drain ion implantation and an annealing process are performed thereto to form a source/drain region 10 on the substrate surface between the gate electrodes 6 including the spacer 9.
Referring to FIG. 1D, silicide 11 is formed on the surface of the gate electrode 6 according to the conventional process to form a transistor 12 and a flat capacitor 13 on a proper position of the substrate 1.
Then, although it is not shown in drawings, a series of post processes including a wiring process are performed so as to manufacture an MDL device.
However, although the conventional method described above can produce MDL devices without performance degradation by use of a logic process and through adaptation of a flat capacitor, the limitation of the chip size causes a limit of the capacity increase of the DRAM capacitor, so that it is substantially difficult to adapt a DRAM of 4M or higher.